PD=0
DDR Control Register 13
| TREFINT | Reserved |
| RESERVED | Reserved |
| PD | Power Down 0 (0): Enable full power state 1 (1): The memory controller completes processing of the current burst for the current transaction (if any), issues a precharge all command, and disables the clock enable signal to the DRAM devices. Any subsequent commands in the command queue are suspended until this bit is cleared. |
| RESERVED | Reserved |